1. Field of the Invention
The present invention relates to assembly master slice semiconductor devices contained in different types of packages and, more particularly, to a semiconductor device using a master slice approach which allows easy identification of bonding pads which can fit specific type of package when bonding wires are connected to the bonding pads.
2. Description of the Related Art
A semiconductor integrated circuit device (to be referred to as an LSI hereinafter) using an assembly master slice approach as a conventional method to improve the developing and production efficiencies o an LSI is known. In this approach, a large number of basic units such as transistors and gate circuits are formed on a semiconductor chip in advance, and wiring layers between the basic units are formed using a mask for forming wiring layers in the final step in the manufacturing process. Therefore, an LSI having a desired function can be manufactured within a short period of time.
In an LSI, e.g., 1M- or 4M-byte DRAM (dynamic random access memory) manufactured by the assembly master slice approach, electric pads called bonding pads are also formed by the master slice approach to be contained in various packages such as of DIP (dual in-line package) type, SOJ (small out-line J lead) type, or ZIP (zigzag in-line package) type. More specifically, bonding pads having the same outer shape are previously formed at positions which fit different types of packages, and surface protective films each consisting of, e.g., an insulating film, are deposited on the bonding pads, respectively. Thereafter, openings for bonding are formed in the surface protective films at all the bonding pad positions using a common mask which fits the different types of packages. Thereafter, only the bonding pads which fit a specific type of package are connected to lead electrodes called inner leads using bonding wires. Therefore, in the LSI of this type, bonding pads which are not bonded are present besides the pads bonded to the lead electrodes.
FIG. 1 is a plan view of a conventional LSI in a ZIP type package. In a peripheral portion of a chip 12 sealed in a package 11, a plurality of bonding pads 13 are arranged in advance at positions which fit different types of packages. As shown in FIG. 1, in the ZIP type package, the bonding pads 13 arranged among three sides of the chip 12 are connected to inner leads 15 through bonding wires 14, respectively.
FIG. 2 is a plan view of a conventional LSI of an SOJ type package. As shown in FIG. 2, in a package 16 of an SOJ type, the bonding pads 13 which are arranged along the two opposite sides of the chip 12 are connected to the inner leads 15 through the bonding wires 14, respectively.
FIG. 3 is a plan view of the chip 12 commonly used for the ZIP type LSI shown in FIG. 1 and the SOJ type LSI shown in FIG. 2. In FIG. 3, a region A hatched by lines inclined from the upper left direction to the lower right direction serves as a pad region for the ZIP type package, and regions B hatched by lines inclined from the upper right direction to the lower left direction serve as pad regions for the SOJ type package. As shown in FIG. 3, the regions A and B partially overlap each other.
The above-mentioned bonding operation is often performed using a self-teaching bonding apparatus. In this apparatus, an operator observes the positions of the bonding pads 13 and the inner leads 15 by a microscope, and sets the bonding positions in the bonding apparatus with reference to a diagram of the bonding positions.
In the conventional semiconductor device using the master slice approach, however, the bonding pads 13 having the same outer shape are arranged on a chip to fit the different types of packages. Therefore, an operator may misidentify pads to be bonded and pads not to be bonded upon observation using a microscope.